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Double-data-rate architecture; two data transfers per clock cycle |
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Bidirectional data strobe [DQ] (x4,x8) & [L(U)DQS] (x16) |
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Differential clock inputs(CK and CK) |
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DLL aligns DQ and DQS transition with CK transition |
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Frequency:266Mhz,333Mhz, 400Mhz |
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Programmable Burst length (2, 4, 8) |
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Programmable Burst type (sequential & interleave) |
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Edge aligned data output, center aligned data input |
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Auto & Self refresh, 7.8us refresh interval
(8K/64ms refresh) |
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Serial presence detect with EEPROM |
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SSTL_2 Interface |
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66pin TSOP II and 60 ball FBGA package |
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All of products are Lead-Free, Halogen-Free, and RoHS compliant |
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PCB Dimension 30.35mm |
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Storage Temperature -55°C ~+150°C |
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Operating Temperature 0°C ~ + 70°C |
DDR-Registered DIMM
Features:
